The present invention relates to the field of instruction-controlled digital computers and specifically to methods and apparatus associated with the channels within data processing systems.
In the prior art, channels have been architecturally defined as that part of the data processing system which serves control units associated with the systems input/output (I/O) devices. Channels have been independent and discrete apparatus having their own set of commands which enable the I/O devices to read and write data while the remainder of the system concurrently processes instructions not necessarily related to I/O devices. Each channel has had its own instructions in system storage which have been fetched and processed under supervisory program control.
Channels are generally of three types, selector, byte multiplexor, and block multiplexor. Selector channels and block multiplexor channels are generally associated with high-speed devices, while byte multiplexor channels are usually associated with low-speed devices. A plurality of I/O devices are connected to a channel through a control unit. Byte multiplexor channels and block multiplexor channels allow interleaved transfer of data from multiple devices attached to the same physical channel interface.
Whle channels function somewhat independently of instructions executed by the data processing system, the data processing system maintains supervisory control over the channel and I/O operations. Channels are therefore processors of information which have some independence from other system processors (e.g., I-unit) and hence increases the concurrency of the processing of information by the system.
While prior art apparatus has worked satisfactorily, there is a need for improved channel apparatus which makes more efficient use of modern high-speed technologies. Whereas I/O devices operate at comparatively limited speeds which limit the maximum data rate over a channel, frequently due to mechanical limitations, and whereas electronic circuits operate at much higher speeds, those circuits desirably should be shared by a plurality of I/O devices in order to make more efficient use of their high speed capabilities. In prior art channel structures in which channel apparatus has been dedicated on a per channel basis, the circuits in one channel have not been readily shared with other channels.